Theflexibleness of the software-translation approach comes at a price:the processor needs to dedicate a number of its cycles to runningthe Code Morphing software; cycles that a traditional x86 processor may use to execute application code. However, the benefits of such an approach way outweigh its limitations.LONGRUN POWER MANAGEMENTIt is a provision in TM5400 model Crusoe that can additionally limitthat processor is as of now low power utilization. .In a mobile setting, most conventional x86CPUs manage their energy utilization by quickly exchanging betweenrunning the processor at full speed and killing the processor. Be thatas it may, the processor might be closed off exactly when a time-critical applicationneeds it.
Conversely, the TM5400 can modify its energyutilization without turning itself off – rather, it alters its clock recurrenceon the fly, without requiring an operating system reboot. Subsequently,programming can consistently screen the requests on the processor also,powerfully pick only the ideal clock speed (and henceforth power utilization) expectedto run the application. The importance ofthe hybrid approach to deal with chip configuration is probably going to turnout to be more obvious throughout the following quite a long while. Theinnovation offers more opportunity to advance (both hardware and software) thannormal hardware-only outline. Nor is the approach restricted to low-powerdesigns or to x86-suited processors. Appliances like mobile computers and net access devices, laptop talents and unplugged running things of up to ona daily basis are offered by Crusoe Processors.CRUSOEPROCESSOR ARCHITECTUREThe Crusoe microprocessoris obtainable in the market in the subsequent variants: TM3120, TM3200, TM5400and TM5600.
The fundamental architecture of all the above models are same asidefrom some minor changes since several models have been presented for severalsections of the mobile computing market. The subsequent architecturalexplanation has taken Crusoe TM5400 as reference. The Crusoe Processor joinsnumber and drifting point execution units, isolate direction and informationstores, a level-2 compose back reserve, memory administration unit, andinteractive media guidelines. Additionally, these traditional processorhighlights, there are some further units, which are typically part of the coresystem logic that encompasses the microprocessor. In mix with Code Morphingprogramming and the extra framework core logic units, the VLIW processor,permit the Crusoe Processor to produce a greatly incorporated, ultra-low power,high performance stage results for the x86 mobile market.Processor CoreThe Crusoe Processorcore design is relatively easy by typical.
It’s upheld ona standards VLIW 128-bit instructionset. At intervals thisVLIW design, the controllogic of the processor is kept basic and software is used to manage the planningof instructions. This enables asimplified and straightforward hardware implementation with an in-order7-stage floating point pipelineand a 10-stage floating-point pipeline. By streamlining the processor hardwareand reducing the control logic junction transistor count, theperformance-to-power consumption ratio relation are often greatly improved overtraditional x86 architectures.Associate degree 8-way set associative Level one (L1) instruction cache, and a16-way set associative L1 data cache are included in the Crusoe Processor.
Itconjointly includes associate degree integrated Level two (L2) write cache forimproved effective memory information measure and increased performance. Thiscache design assures most internal memory information measure for performanceintensive mobile applications, maintaining a similar low-power whereasapplications, implementation that has a superior performance-to-power consumption magnitude relation relative to previous x86implementations. Other than having executionh/w for logical, arithmetic, shift, and floating purposeinstructions, as in typical processors,the Crusoe has terribly distinctive optionsfrom ancient x86 styles. To ease the interpretation method from x86 to the core VLIW instructionset, the h/w generates a similar conditioncodes as typical x86processors and operates on asimilar 80-bit floating-point numbers. Also, the TLB has the sameprotection bits and address mapping as x86 processors.
The s/w element of this solution is employed to emulate all alternative options ofthe x86 design. Thesoftware that converts x86 programs into the core VLIW directions is that the CMS.Integrated DDR SDRAM Memory ControllerDDR SDRAM interface is that the highest performancememory interface accessible on the Crusoe. The DDR SDRAM controller supportsonly Double Data Rate(DDR) SDRAM andtransfers data at arate that’s double the clock frequency of theinter-face. This feature is absent within the model TM3200. The DDR SDRAMcontroller supports up to 4 banks, the equivalent of 2 Dual In-line MemoryModules(DIMMs) of DDR SDRAM employing a 64-bit wide interface. The DDR SDRAMmemory are often inhabited with 64M-bit, 128M-bit,or 256M-bit devices. The frequency setting for the DDR SDRAM interface isinitialized throughout thepower-on boot sequence.
Integrated SDR SDRAMMemory ControllerThe SDR SDRAM memorycontroller supports up to four banks, equal to2 small Outline Dual In-line Memory Modules(SO-DIMMS), of Single Data Rate(SDR) SDRAM which will be designed as64-bit or 72-bit SO-DIMMs. These SO-DIMMs can be inhabited with 64M-bit, 128M-bit or 256M-bit devices. AllSO-DIMMs should use a similarfrequency SDRAMs, however there aren’t any restrictions on mixing completelydifferent SODIMM configurations into every SO-DIMM slot. The frequency settingfor the SDR SDRAM interface is initialized throughout the power-onboot sequence.Integrated PCI ControllerThe Crusoe Processorincludes a PCI bus controller that’s PCI 2.1 compliant. The PCI busis thirty two bitswide, operates at thirty three MHz, and is compatible with 3.
3V signal level. It’s not 5Vtolerant, however. The PCI controller on provides a PCI host bridge the PCI busarbiter, and a DMA controller. Serial ROM InterfaceTheCrusoe serial ROM interface could be a five-pininterface used to browse data froma serial flash ROM.The flash ROM is 1M-byte insize and provides non-volatilememory for the CMS. Throughout theboot method, the CodeMorphing code is traced fromthe ROM to the Code Morphing memory area in SDRAM.
The Code Morphing code needs eight to 16M-bytes of memory area once it is moved.