HYPER-THREADING: can be individually interrupted, directed to execute a

HYPER-THREADING:Hyperthreading (called as hyper-threading technology) is Intel’s trademark simultaneousmulti-threading (SMT) implementation to improve computational parallelizationdone on x86 microprocessors. (a)           HISTORY: The concept behind this technology was patented by SUNMICROSYSTEMS.

It was first introduced in 2002 in certain Intel’s Pentium 4 andXeon processors, however it was discontinued because the processors were unableto support it and it was afterwards integrated in Nehalem architecture ofprocessor which is the basis for all current core i3, i5, i7 processors.  (b)           OS REQUIREMENTS: The operating system utilizing hyper-threading mustbe capable of simultaneous multiprocessing (i.e. the capability of dividingwork load among multiple processors), it should have SMT support and should bespecifically optimized for it, however the technology is transparent to theoperating system and program.(c)           FUNCTIONALITY: It allows a single microprocessor to act as twoseparate microprocessors to the operating system i.e. for each physical corethe operating system addresses two logical (virtual) processors and shares thework load between them, each of which can be individually interrupted, directedto execute a thread, halted. It uses the processor’s resources (both thelogical processors share the same resources such that when one of the logicalprocessors is stalled the other can borrow its resources) more efficiently byenabling multiple threads to run at a time.

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The main function of it is toincrease the number of independent instructions in a pipeline. Withhyper-threading, the physical processor can execute more than one concurrentstreams of instructions sent by the operating system, allowing more work to bedone in each clock cycle by the processor. Hyper-threading is efficientlyapplicable in those situations where multi-tasking with heavy software’s (suchas Maya, Unreal Engine, 3d editing, gaming etc.) is required. In such cases,the tasks are scheduled in such a way that there is no idle time on theprocessor, it can also push light software’s all in one processor and the heavysoftware’s in others.

(d)           BENEFITS: One of the features of this technology include increase inprocessors throughput and an improvement in performance of threaded software’s.One can run demanding applications along with maintenance of systems responsiveness.It allows us to do intensive graphics without compromise.  According to Intel, the first hyper-threadedprocessor used 5% more die area than a non-threading one but the performanceboost was of about 15-30%, however in general performance boost is mostapplication dependent.  (e)           DRAW-BACKS: Hyper-threading is inefficient in situations where tasksare being performed sequentially i.

e. in a serial manner in the beginning, theoperating systems were not optimized for hyper-threading.  Hyper-threading was also criticized forincrease in heat output and power consumption. In 2017, it was revealed thatsome of Intel’s processors had a bug with their hyper-threading implementationwhich could cause data loss.                                                                                                      Windows canschedule two different threads on one physical core at the same time if thephysical core is working on the first task but still has some resources free itcan go ahead and use its remaining resources to process the second task so youwon’t always have a clean doubling or halving of performance if you’re runningone thing versus two but you will see substantial performance differences ifyou’re leveraging the hyper threading feature on a physical core but there isno real distinction to draw between the logical cores on a hyper-threading cpu,they are all the same thing both physically and how a hyper threading aware OSlike Windows 10 sees them.                                                                                              CLOCK-GATING:In computersystems, many a times data is loaded in registers very infrequently, yet theclock signal toggles after every clock cycle, the clock signal often drives alarge capacitive load leading to dynamic power consumption.

Clock gating addsmore logic to prune the clock tree which disables portions of logic circuitrynot in use at that time so that the flip flops in it do not have to changestates since power consumption is mostly due to the switching of states of flipflops, one of the main advantages of clock gating are reduced die area as lockgating logic removes a large number of muxes from the circuitry. Insemiconductor microelectronics, clock gating is a power-saving technique usedfor switching ON and OFF of circuits. In literal meanings Clock gating is atechnique of saving power by stopping clock to a logical unit when it is notoperating   Clock gating is efficientlyused by many devices to turn off buses, controllers, bridges, and parts ofprocessor, to reduce power consumption.Clock gatingcan be done in two ways, either by software switching of power states perinstructions or through smart hardware that determines whether that specificcircuitry is further required, if not, then switches it OFF, or a combinationof both. It works by grouping circuits into logical blocks, such that when nowork is being done, they are shut off. Power consumption in asynchronouscircuits is usually data-dependent as they by definition do not have a “clock”.Clock gating can be done by using an AND gate with negative level sensitivelatch or with OR gate along with positive level sensitive latch, the benefitsof which are zero cycle hold check and no additional latency , this idea gaverise to Integrated Clock Gating Cell. Integrated Clock Gating Cell is of twotypes i.

e. AND type ICGC and OR type ICGC.(a)           AND type ICGC:It has an AND gate preceded by negative levelsensitive latch. The enable and test-enable are set to active high, theclock-out however has an inactive low state. (b)           OR type ICGC:It has an OR gate preceded by positive levelsensitive latch. The enable and test-enable are set to active low, theclock-out however has an inactive high state.

During theshift in scan testing, all the clock control functions have to be bypassed tolet the shift happen, in ICGC we have test-enable input for that matter i.e.whenever the design has to go in shift mode, the test-enable signal goes high,thereby bypassing all the functional enable signals  IVY BRIDGE:IvyBridge is the code name of third generation Intel core processors.

These CPU’spart numbers begin with 3. Ivy Bridge uses some newer technologies. In order toachieve the reduction in Ivy Bridge die size, Intel developed a new kind ofthree-dimensional “Tri-Gate” transistor Mass production of Ivy Bridge chipsbegan in the third quarter of 2011. Dual-core mobile models were launched on 31stMay 2012 whereas quad-core mobile models were launched on 29th April2012. However core i3 processors were available in market by September 2012.The socket used for Intel microprocessors based on ivy bridge microarchitectureis called socket H2 LGA 1155.

Ivy bridge microarchitecture somewhat resemblesits predecessor Sandy bridge but has more processing power and slightly lessphysical size. Almost all ivy bridge chips are quad-core (except for economyversion), having clock speeds ranging from 2.5 to 3.5 GHz (giga bytes) alongwith a cache size of 6 to 8 MBs (megabytes). The ivy bridge processors employ a22nm architecture that is drop in physical size approximately one-thirdrelative to previous chips. They are also backward compatible with sandy bridgeprocessors. The advantages of ivy bridge microarchitecture are (1) support forPCI Express3.0 and DDR3L memory (2) enhanced security features (3) replacementof DirectX 10.

1 with DirectX11 capabilities (4) smaller microprocessor yieldingspace for integrated graphics chip hence improving display performance, up tothree displays are supported (5) Multiple 4K video playback (6) A 14-19 stageinstruction pipeline (7) the built-in GPU has 6-16 execution units. THROUGHPUTIntelincreased the throughput of the floating-point and integer dividers in IvyBridge as opposed to Sandy Bridge so when you’re doing floating-pointoperations they have twice the throughput as sandy bridge which means thatfloating point calculations should be able to gothrough more quickly. ULTRAPERFORMANCE CONFIGURABLE TDP: The nextthing that’s closely related to process manufacturing is the thermal designpower or TDP of the processor. TDP is a measure of how much cooling you’regoing to have to put into the chip so what this means is that Intel guaranteesthe manufacturers that if it dissipates a certain amount of heat the CPU willoperate as intended for example if your processor has a 35 watt TDP that meansthe manufacturer has to ensure that they can dissipate 35 watts of heat, if yougo over that thermal limit and if you don’t dissipate 35 watts of heat theprocessor is not going to be able to run at full speed so the lower the TDP theless design effort that’s required to cool the chip down to make sure that youoperate as fast as possible  POWERAWARE INTERRUPT ROUTINGIvy bridgehas another feature called power-aware interrupt routing and what thatbasically means is that if there are two out of four cores active what it doesis that it looks at the instruction stream and says which core should I sendthis to that are active so it’s only going to send instructions to the activecores instead of like rotting it to inactive cores in this way we don’t have towake up inactive cores and just keep it through cores that are currentlyactive, hence a lot of energy will be saved.  OVERCLOCKING THERMAL ISSUES:Ivy bridges temperatures are reported to be ten degreeCelsius higher than sandy bridge.  SANDY BRIDGE:Sandy Bridge is the code name of second generation Intelcore processors.

These CPU’s part numbers begin with 2. Its first productsunder the Core brand were released in January 2011. It was developed primarilyby the Israeli branch of intel codenamed Gesher (“bridge” in herbrew). Sandybridge implements 32nm manufacturing process. .they generally comes up in thirdgeneration of Intel core processors.

They have launched it after their Nehalemseries of processorsArchitecture of sandy bridge consists of more than one coresthat increase the speed of processing and execution of programs using theterminology known as hyper threading.This hyper threading is basically a technology that isadopted by Intel company in their computers where a single microprocessor actlike two separate processors for the operating systems and all the consoleapplications. With this hyper threading core of a microprocessors executeprograms simultaneously.They are generally managed by clock signal.

it simplyinvolves the division of the load of work by the group of cores amongthemselves in Intel computer architecture.Now talking about the internal consistency of  sandy bridge, it consist of about 2 billiondouble gate transistors on each of the processor with having eight to nine cores on a single board.Sandy bridge is common in models of Intel computers likeCore i3, Core i5 and Core i7. Each of these models have processors with maximumclock speed of 2 G Hz.

They have the ability of video decoding and the encodingthem too. It contains all graphic cores and cards on a single chip.Intel had manufactured sandy bridge using die fabricationtechnology. Sandy bridge processors are built for laptops, workstations,desktop and other server computers working in huge institution.The most advanced and up to date sandy bridge has four coresmaking it quad processor.Each core has two level of cache line memory.

It is a bigadvantage for the processor while executing it can fetch and store data withinitself thus reducing latency as compared to other models of computers. Theyalso have third level of cache line memory which is utilizes for the communicationand receiving instructions.