ABSTRACTThis these devices in a variety of applications (physics).

ABSTRACTThis report presents the pattern transfer of amorphous silicon thin film transistors (TFTs) using the UV (365 nm wavelength) photolithography technology. The lab pattern transfer process involves photoresist for wafer spinning, UV exposure using the mask aligner, and photoresist development. The first lithography level is defining the n-type amorphous silicon area, which is Chrome Metal Gate structure. The second lithography level is defining the metal contacts, which is Source-Drain Metal structure patterned onto amorphous silicon.INTRODUCTIONThin-film-transistor (TFT) technology is a well-known technology widely used in flat-panel displays, computers, smart phones, video game systems, and personal digital assistant. (Japan). There has been an enormous amount of activity, worldwide, that has resulted in the utilization of these devices in a variety of applications (physics). TFTs are MOS devices with a deposited film used as channel materials and as gate dielectrics. The most common channel material is amorphous silicon, a: Si: H.A TFT is a type of field–effect transistor made by depositing thin layers of a semiconductor, a dielectric, and metallic contacts. Traditional transistors use the substrate as the semiconductor material. The substrate used in TFT is independent. The TFT has four layers. The first layer is the chromium layer called the “gate” also refers to the first film deposited and patterned on the substrate. The substrate is typically a silicon wafer with thermal oxide grown with thermal oxidation. The dioxide layer is the insulating film on top of the chrome, which is to avoid any current flowing from transistor to the ground. The dielectric, silicon nitride, is the second layer. The semiconductor, amorphous silicon, is the third film deposited with PECVD. The source/drain layer is the last film deposited to the amorphous silicon.In addition to the purpose stated above, the subject of this paper also includes, understanding of lithography process. In this process, a pattern is transferred to a photoresist by exposure to a light source through an optical mask. A structure is patterned which has specific dimensions. The pattern structure is not usually the same size as the mask. One mask has to be aligned with the structures already there. These dimensions influence the behavior of the transistor. In our lab work, we discuss what happens if we pattern the gate structure larger or thinner, and in which way it influences the behavior of the transistor. We deal with an optical mask consisting of opaque patterns chrome on a quartz transparent support used to define features on a wafer. After this process, it is expected that the pattern in the photoresist is transferred to the underlying substrate by etching or deposition techniques. The combination of accurate alignment of a successive set of photomasks and exposure of these successive patterns lead to complex multi-layered structures. The photolithography is performed on a contact aligner using positive photoresist and negative resist. The microscope images of the dimensions of the patterned structures are recorded, and the shapes after the development are demonstrated. The report shows the relevant background on device photolithography technology, including recent developments based on a recently published survey. Finally, the report includes the presentation of our experimental data and the discussion of lab reports findings.LITERATURE REVIEWConventional lithography process possesses challenges in manufacturing. Some of the challenges are the misalignment of the mask, the choice of contact modes, overexposure of the resist, overdevelopment of the wafer, low resolution. Some of these challenges have been highlighted and their effects are described in the literature. Recent trends include digital lithography, extreme light lithography. These points are used in these report in the discussion and results section mainly because some of the challenges have been encountered while doing the lithography session. A recent report suggested that the use of jet-printed lithography, a process in which TFT features are patterned through the ink-jet printing of a phase-change material, eliminated the exposure and development process required in conventional lithography. (digital).This is done by using a phase change material which enables the feature size to be controlled by the substrate temperature rather than by the wetting properties. The advantage of the digital-lithographic process over conventional lithography is the strength to precise the alignment of mask layer through image processing before patterning. The layer alignment process involves locating the process wafer in the direction of the previously designated layer. By combining jet-printed lithography with digital imaging and processing, a novel patterning process, digital lithography, can be used to register virtual masks for TFT device patterning. A microscope captures the coordinates of the alignment marks. Before printing the mask pattern. The digital process of the mask later performed by repositioning and aligning to the process wafer thus waving the demand for fixing a mask aligner and process wafer mechanically or using optics.EUV lithography, in which high-energy photons with a wavelength of 13.4 nm (100 eV) are used to pattern resists, is one of the leading candidates for next-generation lithography. (recent progress). The idea of EUV lithography is to use small NA reflective optical systems at wavelengths much shorter than the circuit dimensions (limits of lithography). This combination of small NA and small wavelength sequence enables to accomplish both high resolution and large DOF (limits of lithography). This done by using reflective elements such multilayer mirrors to create reflectivity and the mask itself is reflective. The mirror frame must be accurate and the deposited in designing multilayer coatings across a wafer with no defects is a challenge for EUV masks due to the absorption of EUV radiation by most materials over a very short range, mostly 20–50 nm. Another challenge is the resist layers are needed to be 1 m in thickness which is also different than the current application of single thick resist layer.FABRICATION PROCESSOverviewWe start with a substrate and deposit a thin gate metal on to the substrate. This gate metal is patterned into desired shapes using a lithography process and which resist is put on the wafer and the resist is patterned into certain shapes and then that resist serves as a mask for the removal of the gate metal producing the gate metal patterned into gate shapes. A gate dielectric is then deposited on to the wafer followed by a thin film transistor active material. These two materials are subsequently patterned again using a lithography process. Once the gate dielectric and thin film transistor material have been patterned and the gate and the photoresist removed a source-drain metal is then deposited on the wafer and the source-drain metals patterned using lithography to produce the final thin film transistor shape. ProcessThe main process is to fabricate TFT on the wafer. We pattern a structure and this structure has specific dimensions. This dimension will influence the behavior of the transistor. What we have is a gate, the pink one below other layers and on this layer, you have the insulating layer, the gate dielectric. The thin film is structured over the gate and the channel forms that region where the gate is. You also have the source and the drain on the active region but you create a channel not on the substrate, it is on the deposited layer.Amorphous silicon is deposited with PECVD. Amorphous silicon will be patterned with photoresist to protect the channel region.We begin with the substrate. The substrate is typically a silicon wafer with thermal oxide grown on the substrate. Before the session, SiO2 is grown with thermal oxidation. Also, you have silicon, the shiny silver one. Now, we need to deposit the gate metal and our case is going to be the chrome layer approximately a 50-nm thick. The dioxide layer is on insulating layer for chrome on top. The reason is that if we want to measure negative transistor, we do not want to have the wafer on the metal chunk. We do not want any current flowing from transistor to the ground. We want to form resist layer on top of the chrome layer so that we form the top gate layer, the pink one. For the first session, the positive resist is used. Everywhere where the light comes in, resist gets removed. The pattern in the photoresist is then further transferred to the underlying substrate by subtractive (etching) or additive (deposition) techniques.The chromium is removed from the regions where the resist has been removed. We use a chromium. Chromium etches added to the container and that is now removing the chromium metal that is now exposed the regions which still have resists on the chromium metal. The chrome will not be removed in those regions so following the etching of the. We use different chrome etchants, a mixture of different acids, for chrome etching.At this stage, we just have chromium metal sitting on our original substrate in the chromium metal has been patterned into the shapes that we’re interested in for thin film transistor applications at this stage and if we were to look under a microscope we would see pattern chromium The resist also removed by SiN4 acid. Then, we form the dielectric layer, because the gate needs to be isolated from the active region of the transistor. That layer is 200 nm. Amorphous silicon is the one for the active region, the green one in the mask.SiO2 is deposited with PECVD. You have chamber, you put the gases in it and it is heated to 300C, O2, Si.Amorphous silicon is deposited with PECVD. Phosphorus is important for doping. PH3 for n-type doping. We put some phosphorus in the chamber with different gases %1 gas mixture with PH3. If we don’t, amorphous silicon will be like silicon thin film where no electrons are moving and there is no current. You need some doping agent in PECVD so that depending on the gases you can create the active region. What we deposited on this layer, we want to structure amorphous silicon. We want to form source and drain region, we also want to form the channel region.We pattern the channel. The channel will form below the gate. After we put the positive resist, we have some amorphous silicon structure. Amorphous silicon is etched by ICP. We must protect patterned AS area with another insulator because usually moisture, any other material, dust will have a negative effect. SiO2 and SiN4.We must open the source and the drain. PECVD. We will pattern the resist and the open the source and drain region. Amorphous silicon will be patterned with photoresist to protect the channel region. This resist will be negative resist because we do not want to have SiO2 over the channel to open source and drain region metal. We will etch through with RIE dioxide layer until the amorphous silicon. ICP?Then we put the metal on top of it. The metal is usually AL, but it could also be Ti. Now we have source, drain, gate and the chrome. There is only one step left. Metal lift is necessary at the end. The chrome is covered. We must put another layer of resist on top of everything. The area will be opened or the contact for the gate.Description of fabrication procedures First Lab SessionThe first step is to put resist on the wafer for the spin coating. The resist is positive resist. Everywhere where light exposed will be strip off in the development step. We spun the wafer 5000 rpm for 30 seconds to create the 1mM thickness of the resist layer. Once you spun the resist on the wafer, the wafer is baked 115C for 1 minute on the hot plate. The solvent gets more solid. There are lots of solvents on the resist and with baking, the solvent gets evaporated. This was done by soft bake. Negative resist requires 2 steps will be explained in the second part.The positive resist we are using does not do any filtering. The light will go through and this wavelength gets through others not. It does not change the path of the light. The exposure dose is 19.40 mW/cm^2. The lens has a specific power. (time). You set up a time and you calculate the intensity from thee.There are variations of contact modes. There 4 modes, soft, hard, proximity, vacuum contact mode. We put the wafer on and expose to the UV light. The important thing is the exposure time. The exposure time is anywhere between 2-7 seconds, our exposure time is 4 seconds.The resist is exposed using the contact aligner which shines ultraviolet light through this mask the mask has opaque regions and clear regions that are clear the ultraviolet light goes through and it impinges on the resist and the resist in those regions will then become soluble in a developer and the opaque regions the resist will not be exposed to ultraviolet light and the resist will not be soluble for regions that were not exposed to photoresist after exposure the resist containing the substrate is placed into a developer and this will remove resist from the regions that were exposed to ultraviolet light.The last step is the development step. The developer we are using MF319. The ideal development time is 30 seconds on the developer and 30 seconds on the H20. What we have done was 40 seconds in the developer and 30 seconds in H20. After development, we used nitrogen gun to clean the wafer.Second Lab SessionFor the second session, what we have is a patterned wafer its SiO2 is etched and evaporated metal everywhere. We have a formed source and drain. For this session, we used a negative resist AZ2070.  Everywhere where light not exposed will be strip off in the development step. We spun the wafer 6000 rpm for 30 seconds to create the 3.7mM thickness of the resist layer. Once you spun the resist on the wafer, the wafer is baked 115C for 1 minute on hot plate. After baking, the crucial point is mask alignment step. For the UV exposure step, we used an additional filter. The exposure time is set for 5.5 seconds and the choice of contact mode was soft contact. A mask aligner allows you the exact positioning of the wafer directed to the mask. Two independent microscopes located on opposite sides of the wafer to determine the alignment. Alignment accuracy should be -1/3 of the minimum linewidth on the wafer. For the development stage, we used AZ726 MIF for the developer and the duration was 90 seconds. Negative resists show an increased erosion of the exposed areas due to a weak cross-linking. Additionally, the wafer is baked 115 for 5 seconds to create a crosslinking. This was done by soft bake. Negative resists show an increased erosion of the exposed areas due to a weak cross-linking. Apart from the lab, a metal lift-off process was done at the end. The covered chrome area is opened for the contact of the gate.Results and DiscussionFig. 1 shows the chrome gate width deposited on the n-type amorphous silicon with the channel length of 102.53 mm. The ideal channel length is 105m. Compared with the ideal channel length there is a decrease in the length of the channel. The exposure time was in the optimal range with 4 seconds however the development was. It was 50 seconds above 10 seconds from optimal time. This decrease in channel length can be seen as a result of the overdevelopment in the development stage. Fig. 2 shows Alignment Markers for aligning the Source-Drain Metal structure to the Chrome Metal Gate layer. As has the length of 20 mm and SD has the length of 20mm. From fig3, it can be seen that there is a dislocation of AS with the length of 4.55m and 2.60 mm. This due to misalignment. Usually, if there are few layers on other layers and one mask has to be aligned with the structures which are already there, there is a misalignment. Generally, the alignment accuracy should be  1/3 of the minimum width. In our case, it is around 1/4 of the width, which is the in the optimum range. drain-source gate and resist. This is the image of the TFT with source,gate and drain. The source-gate overlap is 1.74  mm and the drain-gate overlap is 7.60 mm. The effective channel length is 9.34mm, gate width (GW) is between the source and drain edge region. The overlapping regions clearly observable and it is not symmetric becasue of overlay misalignment in the second step of photolithography. Overexposure and overdevelopment of the photoresist can be favtors for the overlapping regions. In our case, the exposure time, 5.5 seconds, and the development time, 95 seconds, were slightly higher than the optimal range, with 0.5 seconds and 5 seconds. They both played a role for the overlapping regions. Amorphous silicon can be seen under SiO2 and is misaligned by 2.06 mm and by 10.8 mm.As the lab results suggest, the optical lithography has the advantage of being an easy process and having a quick exposure time, however, the main challenge lies in the alignment process. The misalignment of the layers and the overdevelopment of the resist are the major results of the conventional lithography process. They are important because they influence the behavior of the transistors, for example, having smaller gate width or higher gate length effects the drain-source current. Furthermore, it changes the I-V characteristics of the transistor. To overcome these problems, digital process lithography can be used since it eliminates the alignment and the development stages. It gives the precise mask alignment option. We have not face any issues with the resolution because we chose to use the contact mode. The resolution, using photolithography, is limited due to diffraction. However, the resolution can be improved with EU-lithography. It would be an option because it allows higher resolution. ConclusionAmorphous silicon thin film transistor is patterned in two lithography steps with microfabrication techniques. The images of Chrome Metal Gate structure and Source-Drain Metal structure was demonstrated. The results show the misalignment of the layers and the overdevelopment of the resist.